The present invention is generally related to the field of mass media information storage devices, and more particularly to circuits for controlling the write current used to drive a thin film write head.
Hard disk drives are mass storage devices that include a magnetic storage media, e.g. rotating disks or platters, a spindle motor, read/write heads, an actuator, a pre-amplifier, a read channel, a write channel, a servo circuit, and control circuitry to control the operation of hard disk drive and to properly interface the hard disk drive to a host system or bus. FIG. 1 shows an example of a prior art disk drive mass storage system 10. Disk drive system 10 interfaces with and exchanges data with a host 32 during read and write operations. Disk drive system 10 includes a number of rotating platters 12 mounted on a base 14. The platters 12 are used to store data that is represented as magnetic transitions on the magnetic platters, with each platter 12 coupleable to a head 16 which transfers data to and from a preamplifier 26. The preamp 26 is coupled to a synchronously sampled data (SSD) channel 28 comprising a read channel and a write channel, and a control circuit 30. SSD channel 28 and control circuit 30 are used to process data being read from and written to platters 12, and to control the various operations of disk drive mass storage system 10. Host 32 exchanges digital data with control circuit 30.
Data is stored and retrieved from each side of the magnetic platters 12 by heads 18, 20 which comprise a read head 18 and a write head 20 at the tip thereof. The conventional readhead 18 and writehead 20 comprise magneto-resistive heads adapted to read or write data from/to platters 12 when current is passed through them. Heads 18, 20 are coupled to preamplifier 26 that serves as an interface between read/write heads 18/20 of disk/head assembly 10 and SSD channel 28. The preamp 26 provides amplification to the waveform data signals as needed. A preamp 26 may comprise a single chip containing a reader amplifier 22, a writer amplifier, fault detection circuitry, and a serial port, for example. Alternatively, the preamp 26 may comprise separate components rather than residing on a single chip.
It is desired to achieve high data rates of greater than 1 Gb/s in the write mode. Conventional solutions use a voltage mode to deliver the write data to an H-current switch in the pre-amplifier 26. This voltage mode, however, is not adequate for high data rates greater than 1 Gb/s since the on-chip interconnection and the loading of inactive channels slows the write data. Conversely, if the current mode is utilized, the current mode typically requires two signal lines to achieve a differential current mode for each channel. Typically, the pre-amplifier 26 can have 1, 2, 4, 8, 10 or 12 channels. Thus, in a servo multi-channel write operation, for a 12-channel pre-amplifier, 24 signal buses would need to be laid out all over the integrated circuit, which disadvantagly increases the die size and increases the layout routing complexity.
Hence, the conventional limitations in write data circuits are that the voltage mode is not fast enough, and in the current mode conventional circuits become complex. In addition, parasitic loading effects of on-chip interconnection on data speeds limits the write data rate. In addition, the capacitance loading effect of inactive channels on the write data signals also limits the use of writing using the current mode.
The present invention achieves technical advantages as a write data circuit selectively utilizing current mode ECL level data when writing to a signal channel, and selectively utilizing a voltage mode ECL level when writing to multiple channels. Advantageously, in a single channel write event, the current mode delivers very fast and sharp write currents to the preamplifier H-switch without performance degradation due to on-chip interconnection. When writing to multiple channels, such as in the servo mode, the servo multi-channel write operation does not need to be very fast, and thus the voltage mode write data is adequate. In addition, both the voltage mode and current mode write data share the same differential interconnection to the heads, which advantageously reduces the die area and provides minimum production cost and reduces complexity. For instance, two lines are utilized for four channels, instead of eight lines.